1. Field of the Invention
This invention relates generally to transistor devices and, more particularly, to self-aligned semiconductor devices having properties similar to doubly-diffused MOS devices.
2. Description of the Related Art
High voltage DMOS (double diffused metal oxide semiconductor) power devices have been developed for silicon technology with an important feature being a self-aligned diffusion of the source and base junctions using polysilicon gate masking to form a planar MOS channel between lateral terminations, as described for example in Y. Tarui, Y. Hayashi and T. Sekigawa, "Diffusion Self-Aligned Enhance-Depletion MOS-IC," Proc. 2nd Conf. Solid State Devices, Suppl. J. Jpn. Soc. Appl. Phys., 40, 193 (1971). High voltage capability is achieved by extending the drift region vertically across a lightly-doped epitaxial region, resulting in a dense layout and a low specific on-resistance having a theoretical lower limit of about 0.1 milliohm-cm.sup.2. Conventional DMOS fabrication methods cannot be implemented in SiC because the dopant diffusivities are negligible in SiC at practical process temperatures. Furthermore, in conventional DMOS techniques, the gate electrode overlaps the drain's top surface termination, contributing to parasitic capacitance and reducing operating frequency.
The article of J. Tihanyi and D. Widman, "DIMOS--A Novel IC Technology with Submicron Effective Channel MOSFETs," Technical Digest of IEEE International Electron Devices Meeting, Dec. 5-7, 1977, Washington, D.C., pp. 399-401, describes a replacement of diffusion with ion-implantation which leads to a doubly-implanted MOS (DIMOS) transistor. These DIMOS transistors have only been described for integrated circuit technology and have been realized by subsequent ion implantation of donors and acceptors using a ramp-shaped polysilicon gate as an implantation mask. The ramp-shaped edge profile is difficult to control during etching, resulting in process complexity and uneven edges. Furthermore, the design does not offer a technique for ensuring a complete overlap of the polysilicon over the channel region.